Design and Development of Reconfigurable Multiprocessor Architecture for Embedded Systems

Abstract

In Today’s world, Embedded systems are the brains of almost all digital and industrial control systems.Modern digital systems demand increasing electronic resources, so the multiprocessor platforms are a suitable solution for them which provides better results in terms of area, speed, and power consumption compared to traditional uniprocessor digital systems. Reconfigurable multiprocessor systems are a particular type of embedded system, implemented using reconfigurable hardware. In this paper, Design methods and challenges are discussed. Advances in FPGA technology are leading to more powerful systems in terms of processing and flexibility. Flexibility is one of the strong points of this kind of system, and multiprocessor systems can even be reconfigured at run time, allowing hardware to be adjusted to the demands of the application. Multiprocessor Systems-on-Chip (MPSoC) represent an important trend in digital embedded electronic systems. Although hardware support for parallel computationis increasingly available in embedded processing platforms, there is a distinct lack of effective software support. One of the most important issues with regards to such systems is communication between processors. Now communication in different controllers can be done mainly by two ways i.e. by using I2C and SPI protocol. But there are some limitations of these two protocols which are discussed in this paper and how it can be overcome by using our proposed protocol. Here, in this project, a new method for communication is proposed for an embedded system having multiple peripherals on the board. The adapted arrangement is parallel and hence is more faster way to communicate. This Paper will provide in-depth description of the Reconfigurable Distributed Computing Arrangement of On-board Multiprocessor Communication for Embedded Systems and will investigate its merits & demerits.