Characterization of Enhancement AlInN/GaN Hemts using Partial P-Type GaN Gate

Dilip Jaiswal¹ , Nandkishor Chavan² , Hemant Pardeshi³ , Swati Sharma⁴

¹ Dept. of Electronics and Telecommunication, Jodhpur National University, Jodhpur, India.
² Dept. of Electronics and Telecommunication, Jodhpur National University, Jodhpur, India.
³ Dept. of Electronics and Telecommunication, Jodhpur University, Kolkata, India.
⁴ Dept. of Electronics and Telecommunication, Jodhpur National University, Jodhpur, India.

Correspondence should be addressed to: pardeshi.ju@gmail.com.

Section:Research Paper, Product Type: Journal
Vol.5 , Issue.3 , pp.95-98, Jun-2017

Online published on Jun 30, 2017

Copyright © Dilip Jaiswal, Nandkishor Chavan, Hemant Pardeshi, Swati Sharma . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
 

View this paper at   Google Scholar | DPI Digital Library

XML View     PDF Download

How to Cite this Paper

1310 Views    424 Downloads    320 Downloads

Abstract :
This work attempts to characterize the Enhancement mode (E-mode) AlInN/GaN HEMT devices implemented using p-GaN gate for getting positive threshold voltage (Vt). The device channel consists of a lattice-matched wideband Al0.83In0.17N and narrowband GaN layers, along with p-GaN layer below the E-mode device. The 2D Sentaurus TCAD simulation is done using the hydrodynamic model. The simulation model is calibrated with the initially published experimental result. A comprehensive, quantitative investigation of transfer characteristics, transconductance, gate capacitance, gate leakage and RF gain for E-mode devices is done. The E-mode device exhibit a Vt of + 1.0 V. This new device exhibit almost similar transconductance characteristics. The E-mode device shows lower off-state leakage current, higher ION/IOFF ratio and lower SS. These results demonstrate the feasibility for fabricating an E-mode AlInN/GaN HEMT device which is extremely desirable for high speed and high-frequency applications.

Key-Words / Index Term :
Enhancement mode (E-mode), HEMT, p-GaN, AlInN/GaN

References :
[1]. J J. Kuzmik, “Power Electronics on InAlN/(In)GaN: Prospect for a Record Performance�, IEEE Electron Device Letters, Vol.22, Issue.1, pp.510-512, 2001.
[2]. L. R. Khoshroo, C. Mauder, W. Zhang, “ Optimisation of AlInN/GaN HEMT structures�, Physica Status Solidi-C, Vol.5, Issue.1, pp.2041-243, 2008.
[3]. F. Medjdoub, J. F. Carlin, M. Gonschorek, “Can InAlN/GaN be an alternative to high Power/high temperature AlGaN/GaN devices?�, International Electron Devices Meeting IEDM-06, CA, pp.1-4, 2006.
[4]. F. Medjdoub, M. Alomari, J.-F. Carlin, “Barrier-Layer Scaling of InAlN/GaN HEMTs�, IEEE Electron Device Letters, Vol.29, Issue.5, pp.422-425, 2008.
[5]. M. Alomari, F. Medjdoub, J.F. Carlinet, “InAlN/GaN MOSHEMT With Self-Aligned Thermally Generated Oxide Recess�, IEEE Electron Device Letters, Vol.30, Issue.11, pp.1131-1133, 2009.
[6]. Z. H. Feng, Y. G. Zhou, S. J. Cai, Kei. May. Lau, “Enhanced thermal stability of the twodimensional electron gas in GaN∕AlGaN∕GaN heterostructures by Si3N4 surface-passivation induced strain solidificationâ€�, Applied Physics Letters, Vol.85, Issue.22, pp.5248-5250, 2004.
[7]. Hiroki, H. Yokoyama, N. Watanabe, T. Kobayashi, “High-quality InAlN/GaN heterostructures grown by metal – organic vapor phase epitaxy�, Superlattice and Microstructures, Vol.40, Issue.4, pp.214-218, 2006.
[8]. A. Dadgar, F. Schulze, A. Diez, “High-sheet-charge – carrier-density AlInN∕GaN field effect transistors on Si (111)â€�, Applied Physics Letters, Vol.85, Issue.22, pp.5400-5402, 2004.
[9]. M. Kanamura, "Enhancement-Mode GaN MIS-HEMTs With n-GaN/i-AlN/n-GaN Triple Cap Layer and High- k Gate Dielectrics", in IEEE Electron Device Letters, Vol. 31, No.3, pp.189-191, 2010.
[10]. W. B. Lanford, T. Tanaka ,Y. Otoki , I. Adesida, “High-performance InP-based enhancement-mode HEMTs using non-alloyed ohmic contacts and Pt- based buried-gate technologies�, Electronics Letters, Vol.41, Issue.7, pp.449-450, 2005,
[11]. K. J. Chen, T. Enoki, K. Maezawa, K. Arai, “Enhancement-Mode AlGaN/AlN/GaN High Electron Mobility Transistor with Low On- State Resistance and High Breakdown Voltage�, IEEE Transactions on Electron Devices, Vol.43, Issue.2, pp.252-257, 1996.
[12]. M. Alomari, "InAlN/GaN MOSHEMT With Self-Aligned Thermally Generated Oxide Recess", IEEE Electron Device Letters, Vol.30, Issue.11, pp.1131-1133, 2009.
[13]. H. Pardeshi, G. Raj, S. Pati, N. Mohankumar, C.K. Sarkar, “Influence of barrier thickness on AlInN/GaN underlap DG MOSFET device performance�, Superlattices and Microstructures, Vol.60, Issue.1, pp.47–59, 2013.