Implementation of LSB Based Steganography Algorithms in FPGA

K. Nandhini¹ , B. Gomathi²

Section:Research Paper, Product Type: Journal
Vol.6 , Issue.5 , pp.32-37, Oct-2018

Online published on Oct 31, 2018

Copyright © K. Nandhini, B. Gomathi . This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
 

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Abstract :
Data hiding is one of the crucial techniques in network security. The word Steganography denotes hiding a confidential message (like audio, image, text, video) in a host signal (like Image, video) such that an onlooker cannot detect the existing content. In this paper data drubbing is takes place by the embedding modules that transmit the data and recovering data by extraction, with and without the concept of pipelining technique and it is realized using Xilinx device Virtex-V. A comparison for the pipelined and non-pipelined mode of data is done for parameter like timing constraints, delay, and memory usage. From the outcome, it is addressed that the data embedding using pipelining mode give better results in terms of very less embedding time compared to the non-pipelined mode. As this data hiding methodology using 4 LSB Steganography algorithm involves only simple operation, it is easy to implement as FPGA chip using Verilog HDL model Language.

Key-Words / Index Term :
Steganography, 4LSB, Xilinx device, Verilog HDL

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